EE 762 - Theory and Design of Digital Computers II
Bulletin Description: Detailed Design of major
components of modern computer architecture; design of controllers, ALUs,
floating point units, caches, and memory management units using a
hardware description language.
Offered: Wi Qtrs.
Credits: U G 3
Prerequisites: EE561 or equivalent; EE562, CIS675, or
equivalent
Course Supervisor: Prof. DeGroat
Links to syllabus, homework, and lectures
Syllabus - Winter 2003
Homework and Project Steps
Homework 1 - Due Monday 13 January
Homework 2 - Due Friday 17 January
Lectures
Current Syllabus Information - Winter 2001
Instructor: Prof. DeGroat
Text: VHDL, Analysis and Modeling of Digital Systems,
by Zain Navabi, McGraw-Hill, 1998
(optional) Computer Architecture and Organization by John P. Hayes,
McGraw-Hill,1988
Course Objectives: The objective of this course is to
introduce the student to the detailed design of the major components of
computer architectures. After a brief review of the major components
common to modern computer architectures, the student will be introduced
to the design of components such as arithmetic logic units, floating
point execution units, logic execution units, register design,
controller design, instruction set design, cache design, and memory
management unit design. At the conclusion of the course the student
should be able to generate the specification for these units and
complete the detailed design of these components from these
specifications down to the gate level design using a modern hardware
description language.
Class and Topic:
1 - Introduction and Course Overview
2 - Introduction to HDLs
3 - VHDL Indroduction
4 - "
5 - Design and Modeling of ALUUs (combinational design)
6 - ..Modeling and Simulation of a Generic Functional Unit
7 - ..Structural ALU Design and Description
8 - ..Behavioral Description
9 - Language Features Overview
10 - "
11 - "
12 - Timing and Concurrency - How HDLUs Model Hardware
13 - Exam #1
14 - Exam Review and continue with new material
15 - Timing and Concurrency (continued)
16 - "
17 - Resolution Functions - Modeling and Simulation of Busses
18 - "
19 - "
20 - Design and Modeling of Floating Point Execution UnitUs
21 - ..Behavioral Description
22 - Exam #2
23 - Exam Review and continue with new material
24 - Structural Description of Floating Point Unit
25 - "
26 - Design and Modeling of Cache Controllers
27 - ..Behavioral Description
28 - ..Structural Description
Final Exam: Monday, March 17, 1:30-3:18Pm
Other References:
VHDL, by Douglas L. Perry, McGraw Hill, 1991
A VHDL Primer, by Jayaram Bhasker, Prentice Hall, 1992
Chip Level Modeling with VHDL, by James Armstrong, Prentice Hall, 1988
IEEE Standard 1076-1987, VHSIC Hardware Description Language, IEEE
Press, 1987
Computer Architecture, A Quantitative Approach, by John L. Hennessy and
David A. Patterson, Morgan Kaufmann, 1990
Digital Systems, Hardware Organization and Design, 3rd Edition,
by Fredrick J. Hill and Gerald R. Peterson, John Wiley, 1987.
Other Links:
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JED 4/23/01