EE720 Low Power Mixed-Signal VLSI Design

TA

tbd

Instructor

Steve Bibyk's Office Hours - Mon, Wed, Fri 3:30-4:30pm, (CL381)or by email appt.

ECE720 Sheets

• Syllabus Win 08
• IEEE Spectrum - Analog Jobs

• Mixed Signal System
• Wireless Sensor Node
• System Decomposition in Wireless Sensor Networks
• Op Amp Performance - High Level Modeling
• from 2nd ed. ece721 textbook
• Analog VLSI & Neural Systems , Boook review in Neuromorphic Engr. newsletter ,
  Analog Cell Layouts , MIT Tech Review Interview with C. Mead ,
  Differential Pair Layouts from textbook
• From A/D design with TopSpice book

• System Design
• Round Trip Design
• Cadence Mixed Signal Middle
• System Design & Language
• Design Flow
• Paradox of Analog Circuit Analysis
• Layout with 3D Geometry

ECE720 Lecture Notes

• Initial Overview
• Preface and TOC for ece720 textbook
• Razavi Chapter 1
• Analog vs. Digital Abstraction
• Analog Modelling Problem
• Textbook Reading Guide: chp. 1 & 3
• Some key Sedra/Smith pages , Some of the online slides
• small signal (linear models) from Large Signal Equs.
• A/D and D/A study guide
• Data Converter Lecture slides

ECE720 Homework

• Homework 1 Due Mon. Jan. 14
• Homework 2 Due Fri. Jan. 25
• Homework 3 Due Fri. Feb. 8
• Homework 4 Due Fri. Feb. 29

Online Textbook answers

Exams

Exam I: Mon., Feb. 11. Open textbook (1) only

Exam II: Fri., Mar. 7. Open textbook (1) only

ECE720 Links

Sample Chapter from Analog and Microprocessor System Design

Project CAD Tools

Setup Cadence See Cadence Tool setup, NCSU ver 1.2. Note item 5, the upgrades to the Mentor Graphics link. You will need CAD tools for the project. For tutorials on how to use Cadence, see the section on Tutorials on the Setup webpage. A specific tutorial from NMSU is given here NMSU Analog Cadence Tutorial

To look at the online (unix) Cadence help system, open up a browser - type (at cmd prompt) mozilla&
and then type cdsdoc&
Click on a topic and it should show up in the browser window.

Quick Start Info for Spice

Mosis ami05 instructional transistor models

CAD Project Description

Cadence VerilogA models of data converters and other analog blocks can be found by defining a library in your
cds.lib file as
DEFINE ahdlLib /opt/local/cadence/IC50/tools/dfII/samples/artist/ahdlLib

Some a/d and d/a models that you can use in the TopSpice demo package are here: dac and adc behavioral spice models

CAD tool use for chip design

One goal of the project work is to get familiar with design flows for chip design. In design, it is helpful to know how to interact with the chip fabrication and testing companies. Also, in EE721 (spring), group chip design projects may send out a chip design for fabrication.
A good source for how to deal with chip fabrication companies (foundries) is at: Chip fabrication broker
The site map at this link shows the scope of know-how that is needed: Mosis site map